RTL Design Engineer, AI HW - Contractor
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are looking for an RTL Analysis Methodology Engineer (Contract) to join our AI core design and verification team. This team is responsible for architecting, developing and verifying the Tensix core. Tenstorrent’s Tensix core is architected to support modern AI workloads for both inference and training use-cases. The general-purpose architecture is also used in many high-performance computing applications. The person should have strong experience in RTL design, EDA tools, git and CI enablement.
This role is hybrid, based out of Santa Clara, Austin, or Toronto.
Responsibilities:
- RTL Methodology Development: Design and implement scalable RTL analysis methodologies, covering areas such as linting, CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), and power analysis.
- Tool Integration and Automation: Integrate EDA tools and scripts for automation of RTL analysis workflows, ensuring repeatability and consistency across design projects. Set up and maintain flow regressions and QA.
- RTL Analysis: Conduct analysis of RTL code to optimize design metrics, including area, timing, power, and clocking structures.
- Collaboration: Work closely with RTL design and emulation teams to define and implement best practices, identifying areas for improvement in the RTL design flow.
Experience and Qualifications:
- Bachelor’s or Master’s degree in Electrical or Computer Engineering, or equivalent practical experience.
- 5+ years of demonstrated experience with ASIC design, tools and methodologies.
- Hands-on expertise with RTL linting EDA tools.
- Proficient in hardware description languages, including Verilog and SystemVerilog.
- Skilled in scripting languages such as Tcl and Python.
- Strong debugging and problem-solving abilities, including experience working with EDA vendors to troubleshoot and resolve issues.
- Excellent communication skills, both verbal and written.
Preferred Qualifications:
- Practical experience with synthesis, pre-silicon power estimation flow, Logical Equivalence Checking (LEC).
- Experience with encryption and obfuscation of RTL for IP delivery to customers
- Experience with emulators
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.
Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.
If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.